1. Field of the Invention
The present invention relates to the field of semiconductor, and particularly to a semiconductor device and a manufacturing method thereof. More particularly, it relates to a method of forming a strained semiconductor channel and a semiconductor device manufactured by the method.
2. Description of the Prior Art
In SiGe semiconductor devices, tensile strained Si layer structure disposed on a relaxed SiGe layer is broadly used. Generally, the composition of the relaxed SiGe layer is represented by Si1-xGex, wherein x∈[0,1].
FIG. 1A shows a schematic view of an atom crystal lattice of the tensile strained Si layer structure disposed on the relaxed SiGe layer. FIG. 1B shows an energy level structure of the tensile strained Si layer structure disposed on the relaxed SiGe layer. As shown in FIG. 1B, a conduction band in the tensile strained Si layer is lower than that in the relaxed SiGe layer, due to a large biaxial tension in the tensile strained Si layer. In such a structure, a very high in-plane mobility of electrons is obtained in the tensile strained Si layer.
Currie et al. described a manufacturing method of the relaxed layer and its performance in Applied Physics Letters (Vol. 72, No. 14, pp. 1718-20, 1998), as shown in FIGS. 2A-2D. FIG. 2A shows a longitudinal percentage distribution of Ge atoms of the relaxed SiGe layer. As shown in FIG. 2A, the percentage of the Ge atoms (Ge atom %) increases from 0% to 100% gradually from bottom to top. That is, the x in Si1-xGex gradually varies from 0 to 1. The relaxed SiGe layer or Ge layer is obtained by growing a super thick (a few microns) SiGe layer on a Si substrate. Further, compressive strain in the relaxed SiGe layer is released by defect generation to obtain a relaxed SiGe layer or a Ge layer, as shown in FIG. 2B.
FIGS. 3A, 3B, and 3C respectively show three conventional method of forming the strained Si channel. FIG. 3A shows a structure of a strained Si/bulk SiGe MOSFET (Metal Oxide Semiconductor Field Effect Transistor). FIG. 3B shows a structure of an SGOI (SiGe-On-Insulator) MOSFET. FIG. 3C shows a structure of an SSDOI (Strained-SiGe-Directly-On-Insulator).
However, in the conventional method of forming the Si channel, it is necessary to form a strained Si blanket layer on the SiGe layer (or buried oxide) before device fabrication, such as shallow trench isolation (STI), gate formation, etc. This results in the following problems in the conventional method of forming the Si channel:                (1) The strained Si blanket layer can suffer loss during the device fabrication. For example, pad oxidation step in STI, sacrificial oxidation before gate formation, various wet chemical cleaning processes all can induce loss of the strained Si blanket layer.        (2) The strained Si blanket layer tends to relax in high-temperature step (i.e. the strain is released). For example, anneal for activating source/drain dopant may cause the strain in the strained Si blanket layer to be released.        